Single Cycle CPU Design and Implementation

I designed and implemented a MIPS compliant single cycle CPU. It used a 32-bit architecture. This CPU is capable of completing the following assembly commands:

• load word
• store word
• add
• add immediate
• subtract
• set less than
• xor immediate
• jump register
• jump and link
• jump
• branch equal
• branch not equal

I worked on this project individually over the course of 2 weeks as a part of the computer architecture class.

For more information, click the read more button to the left. (Full Paper)